I. Field
The present disclosure is generally related to circuit devices and methods of measuring clock jitter.
II. Description of Related Art
In general, the temporal stability of a clock signal within a circuit device can impact performance, particularly within synchronous digital circuit devices. Short-term clock fluctuations, or clock jitter, can degrade system performance due to a hazard of timing constraint violations. Clock jitter introduces a parametric yield limitation in circuit devices, because the clock jitter affects the maximum frequency at which core processors can operate. Conventionally, a reduction in the processor frequency can be difficult to measure accurately, in part, because insertion of measurement points may also perturb the clock signal. For example, external test probes measuring clock jitter may perturb the clock signal by introducing capacitances, inductances, impedance mismatches, and other anomalies that can introduce additional clock fluctuations.
To measure clock jitter more accurately, on-chip test structures have been added to circuit devices. On-chip test structures can include a large number of flip-flops to capture a clock value at multiple sampling points along a delay chain. However, to accurately sample the clock signal, a large number of sampling points and therefore a large number of flip-flops are used. The large number of flip-flops can occupy significant area of the overall circuit. Further, accuracy associated with such test structures is typically limited to the insertion delay of each element of the delay chain. For example, if each element in the delay chain has a 20-picosecond delay, the accuracy of the measurement taken between elements in the delay chain may be limited to plus or minus 20 picoseconds. In processor circuits that operate at frequencies in excess of a one Gigahertz, a 40-picosecond delay margin can represent a significant amount of uncertainty in the detected clock jitter, which may be addressed by adding an operating margin that is greater than the detected clock jitter uncertainty margin. This operating margin limits the frequency at which the circuit device can operate.
Further, once clock jitter in a particular circuit design is measured, it remains difficult to determine whether a design change may reduce jitter. While an excessive jitter margin may increase area usage of a circuit substrate, increase power consumption, and increase a time to market for a particular design, an insufficient jitter margin may result in reduced quality and increased number of failures or reduced yield. Hence, there is a need for improved circuit devices and methods of measuring clock jitter.